1. Field of the Invention
The present invention relates generally to a data variation detecting system. More specifically, the invention relates to a data variation detecting system which monitors a portion, on which a control information is multiplexed, in a sequence of data, and modifies a control on the basis of a new control information when data in a monitored zone is varied.
2. Description of the Related Art
FIG. 7 is a block diagram showing one example of the conventional data variation detecting system. The conventional data variation detecting system includes a shift register 61 for taking data within a monitoring zone from a series of input data (DATA) as an n-bit (n is positive integer) parallel data, a data holding circuit always storing a most recent parallel data taken by the shift register 61, an interface circuit (CPUINTF) having a memory (not shown) temporarily storing the parallel data stored in the data holding circuit 62, a processing unit (CPU) 64 exchanging data with the interface circuit 63, and a timing generator 65 generating a timing of the monitoring zone and data holding.
By a timing signal TIM1 generated by the timing generator 65, the n-bit input signal SD1 to SDn of the monitoring zone is stored in the shift register 61. Then, the n-bit input signal is stored in the data holding circuit 62 by a timing signal TIM2. Then, the data LD1 to LDn stored in the data holding circuit 62 is input to the processing unit 64 via the interface circuit 63. It should be noted that TIM input to the timing generator 65 are timing pulses indicative of the monitoring zones in a series of data, and CLK is a reference clock of the data.
On the other hand, the processing unit 64 is designed to perform transmission and reception of signal per m bits (m is positive integer, and is a number establishing (n/m)=integer). Accordingly, the processing unit 64 performs data request for (n/m) times for the interface circuit 63 in order to take n bits of data.
On the other hand, the reference sign RE denotes a read enable signal for a bus, the reference sign WE denotes a write enable signal for the bus, and the reference sign ARE denotes an address output timing signal, respectively.
FIG. 8 is a memory map chart in the interface circuit 63. FIG. 8 shows that the input data is stored in different addressed per m bits. Then, these data LD1 to LDn are output to the processing unit 64 according to control of the RE, WE and data D1 to Dm.
Next, the operation of the processing unit 64 will be discussed. FIG. 9 is a flowchart showing operation of the processing unit 64.
Referring to FIG. 9, a timer interrupt generating portion which is provided in the processing unit 64, generates a timer interrupt in a period longer than the monitoring zone (step 100) and whereby start operation (step 101).
Next, the processing unit 64 obtains the monitoring zone data from the interface circuit 63 (step 102). The memory map in the interface circuit 63 is provided a structure as shown in FIG. 8. Therefore, the processing unit 64 issues read instruction for (n/m) times in total in order to obtain all data in the n bit of monitoring zone.
Next, the processing unit 64 makes judgement whether the currently obtained data is consistent with the data on the obtained in the immediately preceding timing (step 103). If the currently obtained data is not consistent with the data obtained in the immediately preceding timing, a inconsistency flag is set ON (step 104), and the data obtained in the immediately preceding timing is updated by the currently obtained data (step 108). Thereafter, process goes end to return (RTN) to other process which has been interrupted by the read instruction (step 109).
On the other hand, when the currently obtained data is consistent with the data obtained in the immediately preceding timing, check is performed whether the inconsistency flag is ON (step 105). If the inconsistency flag is OFF, the data obtained in the immediately preceding timing is updated by the currently obtained data (step 108). Thereafter, process goes end to return (RTN) to other process which has been interrupted by the read instruction (step 109).
If the inconsistency flag is ON, the inconsistency flag is reset to OFF (step 106). At this time, the processing unit 64 judges that the monitoring zone data is varied to execute operation on the basis of the data obtained at step 102, namely on the basis of the most recent control information (step 107). Then, the data obtained in the immediately preceding timing is updated by the currently obtained data (step 108). Thereafter, process goes end to return (RTN) to other process which has been interrupted by the read instruction (step 109).
Here, only when the currently obtained data is consistent with the data obtained in the immediately preceding timing (step 103), and at that timing, the inconsistency flag has already ON (step 105), judgment is made that the monitoring zone data is varied. This is because that only setting ON of the inconsistency flag is not sufficient for accurately detect variation of data for possibility of occurrence of data error on a transmission line.
Accordingly, once the compared data becomes inconsistent to cause setting ON of the inconsistency flag, and, in the subsequent comparison, the compared data are consistent with each other, inconsistency is judged and whereby variation of data is judged. Namely, the conventional technology has been worked out under the premise that the same data is sequentially input for two or more times.
On the other hand, Japanese Unexamined Patent Publication No. Showa 63-193780 discloses a circuit, in which CPU is operated on the basis of data obtained by a separation circuit.
In the shown circuit, when a vertical synchronization pulse separated by a vertical synchronization pulse separation circuit is supplied to a latching circuit and CPU, respectively, an output of a counter circuit is latched, and the counted output of the counter circuit is input to CPU through a data bus.
In CPU, judgment process is performed on the basis of the counted value at the timing of the preceding vertical synchronization pulse and the timing of the current vertical synchronization pulse. Thus, the vertical synchronization pulse is output as effect when the result of judgment satisfies the predetermined condition.
However, these conventional data variation detection system performs detection of the data variation in the processing unit. Therefore, a period required for this process reduces a period for other processes to cause lowering of process performance of the processing unit.
On the other hand, upon comparison, it is necessary to store the data obtained in the preceding timing in the processing system to require extra memory region for storing such data.
Furthermore, since variation of data is performed by timer interrupt, variation of data can be detected only at the predetermined timing for timer interrupt.